Sachen Mappers -------------- Mapper #143, Sachen's pathetic copy protection Boards: TC-A001-72P (Dancing Blocks) SA-014 (Magical Mathematics) The games are just NROM games (i.e. mapper 0) however they have a pathetic form of copy protection in them. When addresses are read that match this mask: A15 -> A0 ------------------- 010X XXX1 XXXX XXXX a hex inverting tristate buffer returns the inverse of A0-A5 on D0-D5, otherwise, it returns open bus. Note that D6 and D7 always return open bus, since the buffer is only 6 bits. Mapper #145 Boards: SA-72007 This is a simple mapper. Unfortunately, Sachen made quite a few of these things, and mapped the bits differently on each. Addresses which match the following mask: A15 -> A0 ------------------- 010X XXX1 XXXX XXXX will write to the mapper register. Only D7 is used to select an 8K CHR bank. PRG is not switchable. Mapper #146 Boards: TC-3015-72P-VX (Silent Assault) SA-016-1M (Twin Eagle) SA-010-1 (Pyramid 2) Works identically to the above, except the bit ordering is different. D0-D2 select an 8K CHR bank, while D3 selects a 32K PRG bank. Mapper #147 Boards: TC-U01-1.5M (Challenge of the Dragon) This one uses a slightly different address decoding: A15 -> A0 ------------------- X1XX XXX1 XXXX XX10 The bit order of the register is totally different yet again. D2 selects a 32 PRG bank, and D3-D6 select an 8K CHR bank. Mapper #148 Boards: SA-004 (72 pin) Mahjong Trap SA-0037 (famicom) Mahjong Trap This cart's banking register accepts writes at 8000-FFFF. D0-D2 select an 8K CHR bank, while D3 selects a 32K PRG bank. Mapper #149 Boards: SA-0036 (Taiwan Mahjong) Identical to the above, except that only D7 is used to select an 8K CHR bank. No other bits are used. Mapper #150 Boards: SA-72008-VX (Jovial Race) Works identical to mapper #146, except the bits are different. D0-D1 select an 8K CHR bank, while D2 selects a 32K PRG bank. Mapper #243 (Sachen 74LS374N) Boards: This mapper is kinda neat. It is like a super simple MMC3, and only has two registers. They are mapped at 4100 and 4101h. It uses the "usual" sachen address decoding scheme tho, which uses the following address mask: A15 -> A0 ------------------- 010X XXX1 XXXX XXXR Where R selects the control register (0) or the data register (1) This thing only uses D0-D2, so everything is done with a 3 bit word. Writing to 4100 selects one of the following registers, then writing to 4101 writes to that selected register. 0 - xxxx xxxx not used 1 - xxxx xxxx not used 2 - xxxx xxxA 64K CHR bank 3 - xxxx xxxx not used 4 - xxxx xxxB 32K CHR bank 5 - xxxx xPPP 32K PRG bank 6 - xxxx xxCC 8K CHR bank 7 - xxxx xMMx Mirroring: Mirroring: this mapper has the usual H, V, and single screen modes as well as an odd "three screen" mirroring mode. M bits: 00 - H 01 - V 10 - "3 screen" 11 - single screen "3 screen" mirroring looks like this: 01 11 Where "0" and "1" are nametables 0 and 1. CHR banking is broken up into 3 registers. Why this was done, I don't know. Selecting an 8K CHR bank isn't too hard though. The bits are arranged as follows: bit: 3210 ---- ABCC (see register description above for bit locations) These 4 bits allows a maximum of 128K of CHR. 74LS374 pinout: (this is a custom Sachen chip, and NOT the TTL octal latch!!!) ------------------ 1 - A15 (PRG ROM) 2 - CIRAM A10 3 - A11 (CHR bus) 4 - ?? 5 - A14 (NES) 6 - A0 (NES) 7 - D0 (NES) 8 - D1 (NES) 9 - A13 (CHR ROM) 10 - GND 11 - A14 (CHR ROM) A15 (CHR ROM) 12 - A15 (CHR ROM) A13 (CHR ROM) 13 - A16 (CHR ROM) A14 (CHR ROM) 14 - D2 (NES) 15 - /A15 (NES) 16 - A10 (CHR bus) 17 - M2 18 - R/W 19 - A8 (NES) 20 - +5V ------------------- Mappers 137, 138, 139, 141: (SA8259A) All 4 of these mappers uses the SA8259A mapper chip. It works similar to the 74LS374N chip (above). SA8259A pinout: ------------------ 1 - A15 (PRG ROM) 2 - CIRAM A10 3 - A11 (NES CHR) 4 - A13 (CHR) 5 - /RD (CHR) 6 - NC 7 - A16 (PRG ROM) 8 - A14 (NES PRG) 9 - A0 (NES PRG) 10 - regA_bit1 11 - D0 (NES PRG) 12 - D1 (NES PRG) 13 - A17 (PRG ROM) 14 - GND 15 - regB_bit0 16 - regA_bit2 17 - regC_bit0 18 - D2 (NES PRG) 19 - regB_bit1 20 - /A15 (NES PRG) 21 - A10 (NES CHR) 22 - A12 (NES CHR) 23 - M2 24 - R/W (NES) 25 - regA_bit0 26 - A8 (NES PRG) 27 - regB_bit2 28 - +5V regA: these three bits are selected via registers 0 thru 3. regB: these bits are selected via register 4 regC: these bits are selected via register 6 The 8259 has the same 3 bit structure and a similar register assignment to the '374. 0 - xxxx xccc 1 - xxxx xddd 2 - xxxx xeee 3 - xxxx xfff - registers 0-3 are mapped to the "regA" pins (see below) 4 - xxxx xBBB - mapped to the "regB" pins 5 - xxxx xPPP - selects a 32K PRG ROM bank 6 - xxxx xxxC - mapped to the "regC" pin 7 - xxxx xMMR - mirroring/bank restrictor The writing sequence on this mapper is identical to the 74LS374N (Above). Writing to 4100 selects one of the 7 registers, and then 4101 loads that register. PRG mapping is very simple, and is identical on all 4 mappers that use this chip. Writing to register 5 will select a 32K PRG ROM bank. that's it. Mirroring works identically to the '374 (above) so read up on it there. bank restrictor bit R is (register 7) is kinda neat. It disables registers 1 through 3 (See below). Registers 0 through 3 are related. They select a 2K CHR ROM page. PPU A11 and PPU A12 select which of the 4 registers will be used (normally), except when the R bit is set. If the R bit is set, only register 0 is used. Register 0 will be used for all 4 2K CHR banks. (Useful for mapper #139 mainly) --- mapper differences: mapper #138: This mapper is the "flat" space mapper. Not many carts used this method. It allows up to 128K of CHR ROM. CHR banking looks like this: (2K banks) 0000: 00BB Bccc 0800: 00BB Bddd 1000: 00BB Beee 1800: 00BB Bfff mapper #141: This is the "4K bank workalike" mapper. It is used on the bulk of the games. It allows up to 256K of CHR ROM. (note: CHR A11 is tied to the CHR ROM) (2K banks) 0000: 0BBB ccc0 0800: 0BBB ddd1 1000: 0BBB eee0 1800: 0BBB fff1 mapper #139: These carts were set up to use 8K CHR ROM banks. They set the "R" bit (see above). (note: CHR A12 and CHR A11 are tied to the CHR ROM) (2K banks) 0000: BBBc cc00 0800: BBBd dd01 1000: BBBe ee10 1800: BBBf ff11 mapper #137: This mapper was only used on one game (Great Wall) and is pretty funky. They used a 74LS253 dual 4 to 1 muxer and a 74LS257 quad 2 to 1 muxer to remap the banks. They basically made the mapper do 1K CHR ROM banks (for whatever reason) on half the PPU graphics address space. The other 4K is hardwired to the last CHR ROM bank. Here is how it maps: (1K CHR banks, highest bit to lowest bit) 0000: 0 0 0 0 0 c2 c1 c0 0400: 0 0 0 B0 0 d2 d1 d0 0800: 0 0 0 B1 0 e2 e1 e0 0C00: 0 0 0 B2 C0 f2 f1 f0 1000: 0 0 0 1 1 1 P1 P0 1400: 0 0 0 1 1 1 P1 P0 1800: 0 0 0 1 1 1 P1 P0 1C00: 0 0 0 1 1 1 P1 P0 Bx, Cx, cx, dx, ex, fx : these are the CHR banking bits (see registers, above) P0 = PPU A10, P1 = PPU A1. Basically, when the PPU accesses 1000-1FFF, it gets the last 4K of CHR ROM. When it accesses 0000-0FFFh, it gets some selectable banks.